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tpu.h

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00001 /*
00002  * $Id: tpu.h,v 1.15 2003/12/07 07:24:53 dhylands Exp $
00003  *
00004  * tpu.h - This file contains the definitions of the lowlevel
00005  * functions used to access the TPU.
00006  *
00007  * Copyright (C) 2001 Mike Panetta
00008  *
00009  * This library is distributed under the terms of the GNU Lesser General
00010  * Public License (LGPL).  You should have received a copy of the
00011  * license along with this library (LGPL.txt); if not, write to
00012  * the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
00013  * Boston, MA  02111-1307  USA
00014  */
00015 
00043 #ifndef __TPU_H
00044 #define __TPU_H
00045 
00046 #include <68332/types.h>
00047 
00049 typedef struct _TPUObject   TPUObject;
00050 
00052 typedef struct _TPUObject * TPUObjectP;
00053 
00055 typedef struct _TPUChannel   TPUChannel;
00056 
00058 typedef struct _TPUChannel * TPUChannelP;
00059 
00063 typedef enum
00064 {
00065     TPU_ERROR_NONE = 0,
00066     TPU_NUMBER_OUT_OF_RANGE,
00067     TPU_CHANNEL_IN_USE,
00068     TPU_CHANNEL_OUT_OF_RANGE,
00069     TPU_ARGUMENT_OUT_OF_RANGE,
00070 } tpu_errno_t;
00071 
00075 typedef enum
00076 {
00077         TPU_CHANNEL0 = 0,
00078         TPU_CHANNEL1,
00079         TPU_CHANNEL2,
00080         TPU_CHANNEL3,
00081         TPU_CHANNEL4,
00082         TPU_CHANNEL5,
00083         TPU_CHANNEL6,
00084         TPU_CHANNEL7,
00085         TPU_CHANNEL8,
00086         TPU_CHANNEL9,
00087         TPU_CHANNEL10,
00088         TPU_CHANNEL11,
00089         TPU_CHANNEL12,
00090         TPU_CHANNEL13,
00091         TPU_CHANNEL14,
00092         TPU_CHANNEL15,
00093 } tpu_channel_t;
00094 
00098 typedef enum
00099 {
00100         TPU_PRIO_NONE   = 0,
00101         TPU_PRIO_LOW    = 1,
00102         TPU_PRIO_MEDIUM = 2,
00103         TPU_PRIO_HIGH   = 3,
00104 } tpu_prio_t;
00105 
00109 typedef enum
00110 {
00111         TPU_PRAM_SLOT0 = 0x0,
00112         TPU_PRAM_SLOT1 = 0x1,
00113         TPU_PRAM_SLOT2 = 0x2,
00114         TPU_PRAM_SLOT3 = 0x3,
00115         TPU_PRAM_SLOT4 = 0x4,
00116         TPU_PRAM_SLOT5 = 0x5,
00117         TPU_PRAM_SLOT6 = 0x6,
00118         TPU_PRAM_SLOT7 = 0x7,
00119 } tpu_pram_word_t;
00120 
00124 typedef enum
00125 {
00126         TPU_PRAM_SLOT0L = 0x0,
00127         TPU_PRAM_SLOT0H = 0x1,
00128         TPU_PRAM_SLOT1L = 0x2,
00129         TPU_PRAM_SLOT1H = 0x3,
00130         TPU_PRAM_SLOT2L = 0x4,
00131         TPU_PRAM_SLOT2H = 0x5,
00132         TPU_PRAM_SLOT3L = 0x6,
00133         TPU_PRAM_SLOT3H = 0x7,
00134         TPU_PRAM_SLOT4L = 0x8,
00135         TPU_PRAM_SLOT4H = 0x9,
00136         TPU_PRAM_SLOT5L = 0xA,
00137         TPU_PRAM_SLOT5H = 0xB,
00138         TPU_PRAM_SLOT6L = 0xC,
00139         TPU_PRAM_SLOT6H = 0xD,
00140         TPU_PRAM_SLOT7L = 0xE,
00141         TPU_PRAM_SLOT7H = 0xF,
00142 } tpu_pram_byte_t;
00143 
00148 typedef enum
00149 {
00150     TPU_FUNC_UNINITIALIZED  = 0,
00151     TPU_FUNC_QOMDO,
00152     TPU_FUNC_QOMPWM,
00153     TPU_FUNC_QOMPULSE,
00154     TPU_FUNC_FQD_A,
00155     TPU_FUNC_FQD_B,
00156     TPU_FUNC_FQDDI,
00157     TPU_FUNC_MCPWM_MASTER,
00158     TPU_FUNC_MCPWM_SLAVE,
00159     TPU_FUNC_PTA_0,
00160     TPU_FUNC_PTA_1,
00161     TPU_FUNC_PTA_2,
00162     TPU_FUNC_PTA_3,
00163 } tpu_func_t;
00164 
00168 struct _TPUObject {
00169         void *  TPUHardware;     
00170         uint16  initialized;     
00171         uint16  channelsInUse;   
00172     uint32  tcr1Freq;        
00173     uint32  tcr2Freq;        
00174 };
00175 
00179 struct _TPUChannel {
00180         uint16            channel_num;  
00181         uint16            initialized;  
00182         void            * TPUHardware;  
00183         tpu_errno_t       errno;            
00184         TPUChannel      * master;       
00185     void        * userData;     
00186 };
00187 
00188 
00200 #define PRAM_ADDRESS(c, p) ( (((c) << 4) & 0xF0) | ((p) & 0x0F) )
00201 
00205 #define set_channel_master(channel, master) (channel->master = master)
00206 
00210 #define channel_shares_tpu(channelA, channelB)  (channelA->TPUHardware == channelB->TPUHardware)
00211 
00212 /* Start of C function declarations */
00213 #ifdef __cplusplus
00214 extern "C" {
00215 #endif
00216 
00226 int tpu_init (
00227         uint16 tpu_num
00228 );
00229 
00242 int tpu_init_extended (
00243         uint16 tpu_num, 
00244         uint16 tcr1p, 
00245         uint16 tcr2p, 
00246         uint16 psck
00247 );
00248 
00257 uint32 tpu_get_tcr1_freq( 
00258     uint16 tpu_num 
00259 );
00260 
00269 uint32 tpu_get_tcr2_freq( 
00270     uint16 tpu_num 
00271 );
00272 
00283 int tpu_init_interrupts (
00284         uint16 tpu_num, 
00285         uint16 iarb, 
00286         uint16 cirl, 
00287         uint16 cibv
00288 );
00289 
00300 TPUChannel* tpu_request_channel (
00301         uint16 tpu_num, 
00302         uint16 channel_num
00303 );
00304 
00315 int tpu_release_channel (
00316         uint16 tpu_num, 
00317         uint16 channel_num
00318 );
00319  
00331 int tpu_set_CIER (
00332         TPUChannel* handle, 
00333         uint16 value
00334 );
00335 
00345 int tpu_get_CISR (
00346         TPUChannel* handle
00347 );
00348 
00358 int tpu_clear_CISR (
00359         TPUChannel* handle
00360 );
00361 
00372 int tpu_set_CFSR (
00373         TPUChannel* handle, 
00374         uint16 function_code
00375 );
00376 
00386 int tpu_get_CFSR (
00387         TPUChannel* handle
00388 );
00389 
00400 int tpu_set_HSQR (
00401         TPUChannel* handle, 
00402         uint16 value
00403 );
00404 
00414 int tpu_get_HSQR (
00415         TPUChannel* handle
00416 );
00417 
00428 int tpu_set_HSRR (
00429         TPUChannel* handle, 
00430         uint16 value
00431 );
00432 
00442 int tpu_get_HSRR (
00443         TPUChannel* handle
00444 );
00445 
00456 int tpu_set_CPR (
00457         TPUChannel* handle, 
00458         uint16 value
00459 );
00460 
00470 int tpu_get_CPR (
00471         TPUChannel* handle
00472 );
00473 
00486 int tpu_write_parameter_word (
00487         TPUChannel* handle,
00488         tpu_pram_word_t entry, 
00489         uint16 value
00490 );
00491 
00504 int tpu_write_parameter_byte (
00505         TPUChannel* handle,
00506         tpu_pram_byte_t entry, 
00507         uint8 value
00508 );
00509 
00522 int tpu_read_parameter_word (
00523         TPUChannel* handle,
00524         tpu_pram_word_t entry,
00525         uint16* value
00526 );
00527 
00540 int tpu_read_parameter_byte ( 
00541         TPUChannel* handle,
00542         tpu_pram_byte_t entry, 
00543         uint8* value
00544 );
00545 
00555 void tpu_perror ( 
00556         TPUChannel* handle
00557 );
00558 
00559 #ifdef __cplusplus
00560 }
00561 #endif
00562 
00563 #endif  /* __TPU_H */
00564 
00565 // vim: ts=4
00566 // vim: sw=4

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